On Wed, May 23, 2012 at 2:40 AM, James Bottomley
<James.Bottomley@xxxxxxxxxxxxxxxxxxxxx> wrote:
>
> I think the sparc version will work for everybody (it will certainly
> work on parisc). The only thing that might be necessary is to add these
> guards:
The sparc version looks pretty generic (hey, it's almost all the x86
version verbatim), but no, there are more details there:
- the alignment checks you noted (would make sense in
<asm/word-at-a-time.h>: maybe an architecture could do a cut-down
version that doesn't do everything needed for dcache word access, but
is still enough for just this)
- the byte counting depends on byte order (more
<asm/word-at-a-time.h> details) and I suspect people wouldn't want to
do it for each byte anyway: even on big-endian I suspect you can find
smarter zero-finding than doing 8 byte tests by doing a "binary
search" with "has_zero()" and shifting.
- the "where is end of address space" is architecture-dependent
(would need some helper inline in <asm/uaccess.h>). And at least FRV
has a *low* address check too, afaik, so the range check is not
*always* just "this is the max address".
but yes, the amount of architecture-specific code is fairly small.
There *might* be some additional detail I missed, but it's still going
to be a matter of small details rather than anything else.
Btw, the x86 version these days actually zeroes the last bytes of the
word-at-a-time copy. It was cheap, since we calculate the proper mask
anyway, and it means that you never copy unspecified bytes from user
space (even when you do overrun things), but it doesn't really
*matter* - we don't really care what crap goes into the rest of the
buffer. I thought it was cleaner that way, though, and if possible I'd
suggest people try to aim for that.
Linus
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