On Tue, 27 Sep 2011 16:29:41 EDT, Mark Salter said: > This architecture supports members of the Texas Instruments family > of C6x single and multicore DSPs. The multicore DSPs do not support > cache coherancy, so are not suitable for SMP. Is there a usage model for the multicore? I know somebody had some patches for "HPC dedicated compute cores" that would just basically run a userspace process and that's it - would those be applicable here?
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