On Thu, 25 Aug 2011, James Bottomley wrote: > >ARM seems to have these LDREX/STREX instructions for that purpose which > >seem to be used for generating atomic instructions without lockes. I > >guess > >other RISC architectures have similar means of doing it? > > Arm isn't really risc. Most don't. However even with ldrex/strex you need two instructions for rmw. Well then what is "really risc"? RISC is an old beaten down marketing term AFAICT and ARM claims it too. -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
