From: Catalin Marinas <catalin.marinas@xxxxxxx> Date: Mon, 10 May 2010 15:00:10 +0100 > 3rd point above would help with the D-cache aliasing. Does the I/D cache > coherency need to be handled differently? On PIPT Harvard architectures, > we don't actually have D-cache aliasing but we may end up flushing too > much in kunmap() just in case such page would be mapped in user space > with executable permission. You can handle this by having an "I-cache clean" bit in the page. When you kmap/kunmap, simply force this bit clear. In update_mmu_cache() or set_pte_at() you'll see when a page gets into userspace with execute permission, and if the I-cache bit is clear you can do the flush then and set the "I-cache clean" bit. -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
