* Nick Piggin <npiggin@xxxxxxx> wrote: > On Thu, Feb 19, 2009 at 01:20:31PM +0100, Ingo Molnar wrote: > > > > * Suresh Siddha <suresh.b.siddha@xxxxxxxxx> wrote: > > > > > On Wed, 2009-02-18 at 11:17 -0800, Ingo Molnar wrote: > > > > * Suresh Siddha <suresh.b.siddha@xxxxxxxxx> wrote: > > > > So what should happen is to move that smp_mb() from the x86 > > > > generic IPI path to the x86 x2apic IPI path. (and turn it into > > > > an smp_wmb() - that should be enough - we dont care about future > > > > reads being done sooner than this point.) > > > > > > Ingo, smp_wmb() won't help. x2apic register writes can still > > > go ahead of the sfence. According to the SDM, we need a > > > serializing instruction or mfence. Our internal experiments > > > also proved this. > > > > ah, yes - i got confused about how an x2apic write can pass a > > _store_ fence. > > And about how smp_wmb() doesn't emit a store fence ;) yeah ;-) Only wmb() emits a SFENCE all the time. Writes are normally ordered so we map smp_wmb() to barrier(). Ingo -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
