Paul, On Wed, Dec 10, 2008 at 5:44 AM, Paul Mackerras <paulus@xxxxxxxxx> wrote: > Andi Kleen writes: > >> When you say counting you should also include "event ring buffers with >> metadata", like PEBS on Intel x86. > > I'm not familiar with PEBS. Maybe it's something different again, > neither sampling nor counting, but a third thing? > PEBS is an Intel only feature used for sampling. However, this time the hardware (and microcode) does the sampling for you. You point the CPU to a structure in memory, called DS, which then points to a region of memory you can designate, i.e., the sampling buffer. Buffer can be any size you want. Then you program counter0 when an event and a sampling period. When the counter overflows, there is no interrupt, the microcode records the RIP and full machine state, and reloads the counter with the period specified in DS. The OS gets an interrupt ONLY when the buffer fills up. Overhead is thus minimized, but you have no control over the format of the samples. The precision (P) comes from the fact that the RIP is guaranteed to point the an instruction that is just after an instruction which generated the event you're sampling on. The catch is that no all events support PEBS, and only one counter works with PEBS on Core 2. Nehalem is better, more events support PEBS, all 4 generic counters do support PEBS. Furthermore,PEBS can now capture where cache misses occur, very much like what Itanium can do. Needless to say all of this is supported by perfmon. Hope this helps. -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
