Nick Piggin writes: > /* turn off LED */ > val64 = readq(&bar0->adapter_control); > val64 = val64 &(~ADAPTER_LED_ON); > writeq(val64, &bar0->adapter_control); > s2io_link(nic, LINK_DOWN); > } > clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state)); > > Now I can't say definitively that this is going to be wrong on > powerpc, because I don't know the code well enough. But I'd be > 90% sure that the unlock is not supposed to be visible to > other CPUs before the writeqs are queued to the card. On x86 it > wouldn't be. Interestingly, there is also a store to cacheable memory (nic->device_enabled_once), but no smp_wmb or equivalent before the clear_bit. So there are other potential problems here besides the I/O related ones. Anyway, I have done some tests on a dual G5 here with putting a sync on both sides of the store in writel etc. (i.e. making readl/writel strongly ordered w.r.t. everything else), and as you predicted, there wasn't a noticeable performance degradation, at least not on the couple of things I tried. So I am now inclined to accept your suggestion that we should do that. I should probably do some similar checks on POWER6 and a few other machines first, though. Paul. -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
