On Wed, 11 Jun 2008, Nick Piggin wrote: > > I can't actually find the definitive statement in the Intel manuals > saying UC is strongly ordered also WRT WB. Linus? Definitive? Dunno. But look in the Architecture manual, volume 3A, 10.3 "Methods of Caching Available", and then under the bullet about Write Combining (WC), it says the writes may be delayed until the next occurrence of a serializing event; such as, an SFENCE of MFENCE instruction, CPUID execution, a read or write to uncached memory, an interrupt occurrence, or a LOCK instruction execution. However, it's worth noting that - documentation can be wrong, or even if right, can be Intel-specific. - the above is expressly _only_ about the WC buffer, not about regular memory writes. Cached memory accesses are different from WC accesses. so in the end, the thing that matters is how things actually work. Linus -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
