On Tue, 3 Jun 2008, Linus Torvalds wrote:
On Tue, 3 Jun 2008, Nick Piggin wrote:
Linus: on x86, memory operations to wc and wc+ memory are not ordered
with one another, or operations to other memory types (ie. load/load
and store/store reordering is allowed). Also, as you know, store/load
reordering is explicitly allowed as well, which covers all memory
types. So perhaps it is not quite true to say readl/writel is strongly
ordered by default even on x86. You would have to put in some
mfence instructions in them to make it so.
So on x86, these could be re-ordered?
writel(START_OPERATION, CONTROL_REGISTER);
status = readl(STATUS_REGISTER);
Well, you have to ask for WC/WC+ anyway, so it's immaterial. A driver that
does that needs to be aware of it. IOW, it's a non-issue, imnsho.
You need to ask for coherent DMA memory too.
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