On Tue, 2008-06-03 at 16:11 +1000, Nick Piggin wrote: > > - readl is synchronous (ie, makes the CPU think the > > data was actually used before executing subsequent > > instructions, thus waits for the data to come back, > > for example to ensure that a read used to push out > > post buffers followed by a delay will indeed happen > > with the right delay). > > So your readl can pass an earlier cacheable store or earlier writel? I forgot to mention that all MMIO are ordered vs. each other and I do prevent readl from passing earlier cacheable stores too in my current implementation but I'n not 100% we want to "guarantee" that, unless we have stupid devices that trigger DMA's on reads with side effects.. anyway, it is guaranteed in the current case. Ben. -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
