* Nick Piggin <npiggin@xxxxxxx> wrote: > Linus's loop I will use for PAE. I'd love to know whether the hardware > walker actually does an atomic 64-bit load or not, though. all x86 natural accesses (done by instructions) are MESI atomic as long as they lie on a natural word boundary. (which they do in the PTE case) while the hardware walker is not an instruction, it would be highly unusal (and i'd claim, inherently broken) for the hardware walker to fetch a 64-bit pte value via two 32-bit accesses from two different versions of the same cacheline. Ingo -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
