On Fri, 2022-09-30 at 17:16 +0200, Jann Horn wrote: > On Fri, Sep 30, 2022 at 12:30 AM Rick Edgecombe > <rick.p.edgecombe@xxxxxxxxx> wrote: > > The reason it's lightly used is that Dirty=1 is normally set > > _before_ a > > write. A write with a Write=0 PTE would typically only generate a > > fault, > > not set Dirty=1. Hardware can (rarely) both set Write=1 *and* > > generate the > > fault, resulting in a Dirty=0,Write=1 PTE. Hardware which supports > > shadow > > stacks will no longer exhibit this oddity. > > Stupid question, since I just recently learned that IOMMUv2 is a > thing: I assume this also holds for IOMMUs that implement > IOMMUv2/SVA, > where the IOMMU directly walks the userspace page tables, and not > just > for the CPU core? Sorry for the delay, I had to go find out. IOMMU behaves similar to the CET CPUs in this regard. Thanks for the question.
