On 1/30/22 13:18, Rick Edgecombe wrote:
> From: Yu-cheng Yu <yu-cheng.yu@xxxxxxxxx>
>
> When Shadow Stack is introduced, [R/O + _PAGE_DIRTY] PTE is reserved for
> shadow stack. Copy-on-write PTEs have [R/O + _PAGE_COW].
<sigh> Another way to refer to these PTEs. In the last patch, it was:
"read-only and Dirty PTE"
and now:
"[R/O + _PAGE_DIRTY]"
> When a PTE goes from [R/W + _PAGE_DIRTY] to [R/O + _PAGE_COW], it could
> become a transient shadow stack PTE in two cases:
>
> The first case is that some processors can start a write but end up seeing
> a read-only PTE by the time they get to the Dirty bit, creating a transient
> shadow stack PTE. However, this will not occur on processors supporting
> Shadow Stack, and a TLB flush is not necessary.
>
> The second case is that when _PAGE_DIRTY is replaced with _PAGE_COW non-
> atomically, a transient shadow stack PTE can be created as a result.
> Thus, prevent that with cmpxchg.
== Background ==
Shadow stack PTEs always have [Write=0,Dirty=1].
As currently implemented, ptep_set_wrprotect() simply clears _PAGE_RW:
(Write=1 -> Write=0).
== Problem ==
This could cause a problem if ptep_set_wrprotect() caused a PTE to
transition from:
[Write=1,Dirty=1]
to
[Write=0,Dirty=1]
Which would inadvertently create a shadow stack PTE instead of
write-protecting it. ptep_set_wrprotect() can not simply check for the
Dirty=1 bit because the hardware can set it at any time.
== Solution ==
Perform a compare-and-exchange operation on the PTE to avoid racing with
the hardware. The cmpxchg is expected to be more expensive than the
existing clear_bit(). Continue using the cheaper clear_bit() on when
shadow stacks are not in play.
> diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
> index 5c3886f6ccda..e1061b9cba6a 100644
> --- a/arch/x86/include/asm/pgtable.h
> +++ b/arch/x86/include/asm/pgtable.h
> @@ -1295,6 +1295,24 @@ static inline void ptep_clear(struct mm_struct *mm, unsigned long addr,
> static inline void ptep_set_wrprotect(struct mm_struct *mm,
> unsigned long addr, pte_t *ptep)
> {
> + /*
> + * If Shadow Stack is enabled, pte_wrprotect() moves _PAGE_DIRTY
> + * to _PAGE_COW (see comments at pte_wrprotect()).
> + * When a thread reads a RW=1, Dirty=0 PTE and before changing it
> + * to RW=0, Dirty=0, another thread could have written to the page
> + * and the PTE is RW=1, Dirty=1 now. Use try_cmpxchg() to detect
> + * PTE changes and update old_pte, then try again.
> + */
I think we can trim that down. We don't need to explain what cmpxchg
does or why it loops. That's way too much detail that we don't need.
Maybe:
/*
* Avoid accidentally creating shadow stack PTEs
* (Write=0,Dirty=1). Use cmpxchg() to prevent races with
* the hardware setting Dirty=1.
*/
BTW, is it *really* a problem with other threads setting Dirty=1? This
is happening under the page table lock on this side at least.
> + if (cpu_feature_enabled(X86_FEATURE_SHSTK)) {
> + pte_t old_pte, new_pte;
> +
> + old_pte = READ_ONCE(*ptep);
> + do {
> + new_pte = pte_wrprotect(old_pte);
> + } while (!try_cmpxchg(&ptep->pte, &old_pte.pte, new_pte.pte));
> +
> + return;
> + }
> clear_bit(_PAGE_BIT_RW, (unsigned long *)&ptep->pte);
> }
