On 4/2/19 3:08 AM, Florian Weimer wrote:
* Michael Ellerman:
I'm a bit vague on what we're trying to do here.
But it seems like you want some sort of "eye catcher" prior to the branch?
That value is a valid instruction on current CPUs (rlwimi.
r5,r24,6,1,9), and even if it wasn't it could become one in future.
If you change it to 0x8053530 that is both a valid instruction and is a
nop (conditional trap immediate but with no conditions set).
I think we need something that is very unlikely to appear in the
instruction stream. It's just a marker. The instruction will never be
executed, and it does not have to be a trap, either (I believe that a
standard trap instruction would be a bad choice).
I assume you want to avoid a standard trap instruction because it would
be common, and so not meet the intent of the RSEQ_SIG choice as being something
that is *uncommon* right?
It is valuable that it be a trap, particularly for constant pools because
it means that a jump into the constant pool will trap.
--
Cheers,
Carlos.
