On Sun, Mar 24, 2019 at 10:23 PM Wu Hao <hao.wu@xxxxxxxxx> wrote: Hi Hao, This looks fine. > > In early partial reconfiguration private feature, it only > supports 32bit data width when writing data to hardware for > PR. 512bit data width PR support is an important optimization > for some specific solutions (e.g. XEON with FPGA integrated), > it allows driver to use AVX512 instruction to improve the > performance of partial reconfiguration. e.g. programming one > 100MB bitstream image via this 512bit data width PR hardware > only takes ~300ms, but 32bit revision requires ~3s per test > result. > > Please note now this optimization is only done on revision 2 > of this PR private feature which is only used in integrated > solution that AVX512 is always supported. > > Signed-off-by: Ananda Ravuri <ananda.ravuri@xxxxxxxxx> > Signed-off-by: Xu Yilun <yilun.xu@xxxxxxxxx> > Signed-off-by: Wu Hao <hao.wu@xxxxxxxxx> Acked-by: Alan Tull <atull@xxxxxxxxxx>
