On 08/31/2018 10:46 AM, Andy Lutomirski wrote: > On Thu, Aug 30, 2018 at 11:55 AM, Dave Hansen >> That little hunk will definitely need to get updated with something like: >> >> On processors enumerating support for CET, the processor will on >> set the dirty flag on paging structure entries in which the W >> flag is 1. > > Can we get something much stronger, perhaps? Like this: > > On processors enumerating support for CET, the processor will write to > the accessed and/or dirty flags atomically, as if using the LOCK > CMPXCHG instruction. The memory access, any cached entries in any > paging-structure caches, and the values in the paging-structure entry > before and after writing the A and/or D bits will all be consistent. There's some talk of this already in: 8.1.2.1 Automatic Locking: > When updating page-directory and page-table entries — When updating > page-directory and page-table entries, the processor uses locked > cycles to set the accessed and dirty flag in the page-directory and > page-table entries. As for the A/D consistency, I'll see if I can share that before it hits the SDM for real and see if it's sufficient for everybody.
