Hello!
These patches address a problem we ran into using parallel displays
with Freescale i.MX53 and i.MX6 SoC's.
In short: We wanted to change the clock signal polarity by using
display-timing in the devicetree description, but the output signal stayed
unchanged.
Parallel displays may have different polarities for clock and data enable
signals. (Clock polarity is also a topic on LVDS displays). This is the
reason why there are some properties in devicetree display-timing [1]
called
* pixelclk-active .. pixel clock polarity
* de-active .. data enable pulse polarity
This properties are correctly represented in struct display_timings [2]
and struct videomode [3] by using enum display_flags [3].
But when it comes to struct drm_display_mode [4] there are no
representations for this.
The properties are "lost in conversion" and never reach imx drm. (or
other drm drivers).
Changing this would be especially important for embedded devices where
parallel(RGB) and LVDS displays are still widely used and drm already
plays an important role.
Following two patches will
1. Introduce representation of clock and data enable polarities
in struct drm_display_mode analog to hsync/vsync signals.
* "drm: add support for for clk and de polarity"
2. Implicitly enable usage of the newly introduced flags in
imx drm (with respect to devicetree compatibility.)
* "gpu: ipu-v3: use clock and de polarity from videomode"
I'm aware that introducing new flags in struct drm_display_mode affects
user space too and therefore has to be considered carefully.
As I'm not really deep in drm user space your suggestions are very
welcome.
best regards,
manfred
[1] Documentation/devicetree/bindings/video/display-timing.txt
[2] include/video/display_timing.h
[3] include/video/videomode.h
[4] include/drm/drm_modes.h
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