On Wed, Aug 13, 2014 at 12:57 AM, Alexei Starovoitov <ast@xxxxxxxxxxxx> wrote: > add BPF_LD_IMM64 instruction to load 64-bit immediate value into register. > All previous instructions were 8-byte. This is first 16-byte instruction. > Two consecutive 'struct bpf_insn' blocks are interpreted as single instruction: > insn[0/1].code = BPF_LD | BPF_DW | BPF_IMM > insn[0/1].dst_reg = destination register > insn[0].imm = lower 32-bit > insn[1].imm = upper 32-bit This might be unnecessarily difficult for fancy static analysis tools to reason about. Would it make sense to assign two different codes for this? For example, insn[0].code = code_for_load_low, insns[1].code = code_for_load_high, along with a verifier check that they come in matched pairs and that code_for_load_high isn't a jump target? (Something else that I find confusing about eBPF: the instruction mnemonics are very strange. Have you considered giving them real names? For example, load.imm.low instead of BPF_LD | BPF_DW | BPF_IMM is easier to read and pronounce.) --Andy -- To unsubscribe from this list: send the line "unsubscribe linux-api" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
