On Wed, Feb 23, 2011 at 10:54:59AM -0700, Grant Likely wrote: > On Wed, Feb 23, 2011 at 11:26:12AM -0600, Scott Wood wrote: > > The eTSEC revision is probeable as well, but due the way PTP is described as > > a separate node, the driver doesn't have straightforward access to those > > registers. > > Ignorant question: Should the ptp be described as a separate node? Well, the PTP Hardware Clock function is logically separate from the MAC function. PHCs can be implemented in the MAC, in the PHY, or in between in an FPGA on MII bus. If the PHC is in the MAC, then it might be wise to implement one driver that offers both the MAC and the PHC. In the case of gianfar, it is not really necessary to combine the PHC into the gianfar driver, since the registers are pretty well separated. Also, given the size and complexity (and churn over time) of the gianfar driver, I decided to keep the PHC separate. Right now, the driver correctly handles all the clock revisions in the boards that I have (mpc8313, mpc8572, p2020ds, p2020rdb). If checking the revision becomes important, then we can always export a function from gianfar to provide this. Thanks, Richard -- To unsubscribe from this list: send the line "unsubscribe linux-api" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
