Re: [PATCH] add delay between port write and port read

["Maciej W. Rozycki" <macro@xxxxxxxxxxxxxx>]

On Wed, 27 Feb 2019, Linus Torvalds wrote:

> > Should "writeb_relaxed" on Alpha also use the barrier?
> 
> I think they should.  Only the double-underscore (__raw_xyz()) ones
> are entirely unordered, the relaxed ones are just unordered wrt
> regular memory and DMA.

 For that reason though we don't have the trailing barrier in the 
`readX_relaxed' accessors in the MIPS port.

  Maciej