On Mon, 20 Aug 2018, Mikulas Patocka wrote: > > A while ago I proposed a set of different MMIO barriers, that some > > systems may require, corresponding to the respective regular memory > > barriers, but in the I/O context. I never got to implementing that > > proposal, but I still think it's the right thing to do and will see if I > > can find some time to try doing that. Right now we have quite a mess with > > that. :( > > The alpha architecture has only two barrier instructions - "mb" that > orders both reads and writes and "wmb" that orders only writes. I've been aware of that. The high-level barriers obviously would have to map to either of those or none as applicable; with the exception of the completion barrier, which would need an MB followed by a read from a suitable location (preferably one that incurs the least further performance hit). NB a typical use case for a completion barrier is to prevent spurious interrupts from happening when a write has been issued to an interrupt controller's mask register to disable an interrupt line on a system where MMIO reads can bypass MMIO writes. In that case we want to have the mask register actually written right away, rather than the write just scheduled ahead of the next MMIO access (which may happen long in the future). Maciej
