On Tue, Dec 01, 2020 at 04:04:04PM +0000, Valentin Schneider wrote: > > Gating this behind this new config only leveraged by arm64 doesn't make it > very generic. Note that powerpc also has this newish "CACHE" level which > seems to overlap in function with your "CLUSTER" one (both are arch > specific, though). > > I think what you are after here is an SD_SHARE_PKG_RESOURCES domain walk, > i.e. scan CPUs by increasing cache "distance". We already have it in some > form, as we scan SMT & LLC domains; AFAICT LLC always maps to MC, except > for said powerpc's CACHE thingie. There's some intel chips with a smaller L2, but I don't think we ever bothered. There's also the extended topology stuff from Intel: SMT, Core, Module, Tile, Die, of which we've only partially used Die I think. Whatever we do, it might make sense to not all use different names. Also, I think Mel said he was cooking something for select_idle_balance(). Also, I've previously posted patches that fold all the iterations into one, so it might make sense to revisit some of that if Mel also already didn.t
