On Sun, Jun 07, 2020 at 08:18:34PM +0200, Hans de Goede wrote:
> The pwm-crc code is using 2 different enable bits:
> 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE)
> 2. bit 0 of the BACKLIGHT_EN register
>
> So far we've kept the PWM_OUTPUT_ENABLE bit set when disabling the PWM,
> this commit makes crc_pwm_disable() clear it on disable and makes
> crc_pwm_enable() set it again on re-enable.
>
> This should disable the internal (divided) PWM clock and tri-state the
> PWM output pin when disabled, saving some power.
...
> +static int crc_pwm_calc_clk_div(int period_ns)
> +{
> + int clk_div;
> +
> + clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ);
> + /* clk_div 1 - 128, maps to register values 0-127 */
> + if (clk_div > 0)
> + clk_div--;
> +
> + return clk_div;
> +}
You can reduce ping-pong format of the series if you introduced this helper in
the patch that adds -1 to clock divisor.
--
With Best Regards,
Andy Shevchenko
