Each vendor has their own way of describing whether a host bridge
supports ATS. The Intel and AMD ACPI tables selectively enable or
disable ATS per device or sub-tree, while Arm has a single bit for each
host bridge. For those that need it, add an ats_supported bit to the
host bridge structure.
Signed-off-by: Jean-Philippe Brucker <jean-philippe@xxxxxxxxxx>
---
v1->v2: try to improve the comment
---
drivers/pci/probe.c | 8 ++++++++
include/linux/pci.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 512cb4312ddd..b5e36f06b40a 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -598,6 +598,14 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge)
bridge->native_shpc_hotplug = 1;
bridge->native_pme = 1;
bridge->native_ltr = 1;
+
+ /*
+ * Some systems (ACPI IORT, device-tree) declare ATS support at the host
+ * bridge, and clear this bit when ATS isn't supported. Others (ACPI
+ * DMAR and IVRS) declare ATS support with a smaller granularity, and
+ * need this bit set.
+ */
+ bridge->ats_supported = 1;
}
struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 3840a541a9de..9fe2e84d74d7 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -511,6 +511,7 @@ struct pci_host_bridge {
unsigned int native_pme:1; /* OS may use PCIe PME */
unsigned int native_ltr:1; /* OS may use PCIe LTR */
unsigned int preserve_config:1; /* Preserve FW resource setup */
+ unsigned int ats_supported:1;
/* Resource alignment requirements */
resource_size_t (*align_resource)(struct pci_dev *dev,
--
2.25.1
