Re: [PATCH] PCI: Blacklist power management of Gigabyte X299 DESIGNARE EX PCIe ports

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On Wed, Dec 05, 2018 at 02:22:14PM +0100, Lukas Wunner wrote:
> On Wed, Dec 05, 2018 at 12:40:29PM +0200, Mika Westerberg wrote:
> > On Wed, Dec 05, 2018 at 10:48:18AM +0100, Lukas Wunner wrote:
> > > Does the root port have a _RMV and/or _SUN object?  We could e.g.
> > > disallow runtime PM for any bridge with _RMV present and the HPC
> > > bit not set in the Slot Capabilities.
> > 
> > Unfortunately it does not have either of those methods :/ It pretty much
> > looks like a "normal root port" from OS perspective.
> > 
> > Below is the ASL related to the root port (RP05) in question:
> 
> The information might be buried in the Device Labeling DSM but I can't
> make sense of it because I only have access to the PCI Firmware Spec 3.0,
> which is too old.

Good point. I have 3.2 but only ones in that _DSM are:

  4 = PCI Bus Capabilities
  6 = LTR Maximum Latency
  8 = Avoid power-on Reset Delay Duplication on Sx Resume
  9 = Device Readiness Durations

Only thing that could be relevant is 4 (PCI Bus Capabilities) but I
don't see anything in the spec saying it could be hot plug capable :(



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