On 11/20/2018 4:42 PM, Keith Busch wrote:
How does that work? If the OS takes control, it sets up MSIs that FW don't react to, and disables system errors through PCIe Root Control. Aren't those sys errs the mechanism FW knows it has something to do, which means the OS can effectively fence it off?
I think this is all implementation detail and doesn't necessarily apply to all firmware-first implementation flavors. Assumptions are: 1. both FW and OS are listening to MSI interrupts 2. FW monitors the system errors Some FF implementation could route the AER interrupt to a higher privilege level. Some other implementation could use INTx or a side-band channel interrupt for firmware-interrupt too. I have seen all 3 except MSI :) and also firmware never monitored the system error bits. I was curious if anybody ever used those legacy bits. Now, I know someone is using it.
