Hi All,
The purpose of this patch is to make BYT/CHT devices which use s2idle
properly enter/reach S0i3 mode when suspended. Specifically BYT/CHT
devices which have an I2C bus connected to the PMIC which the kernel
shares with the SoC's PUNIT.
Some background info, recently commit a09c59130688 ("ACPI / LPSS: Avoid PM
quirks on suspend and resume from S3") got added to the acpi_lpss.c code:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a09c59130688
We quicky got a couple of reports that this commit had an interesting
unintended side-effect, BYT and CHT devices with the shared bus now all
of a sudden where showing residency in S0ix modes including S0i3.
This was happening because the conditions for lpss_iosf_enter_d3_state()
never become true on those devices and after this commit
lpss_iosf_exit_d3_state() was a nop unless lpss_iosf_enter_d3_state()
executed successfully first.
This did trigger an issue in another part of the kernel, but that got fixed
soon afterwards, see commit 9d9a152ebaa8 ("i2c: designware: Re-init
controllers with pm_disabled set on resume"):
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9d9a152ebaa8
Yesterday another acpi_lpss.c change landed fixing a regression caused
by the other acpi_lpss.c change: commit f11fc4bc669b ("ACPI / LPSS: Force
LPSS quirks on boot").
This makes lpss_iosf_exit_d3_state() run at least once, restoring
BYT and CHT devices with the shared bus to their old state of not reaching
any S0ix states at all.
So this is where this patch comes in, this whole adventures has thought
me (us) that on devices where the I2C bus is shared with the PUNIT the
I2C controller never gets put in D3 (at least not by us), the ACPI
_PS3 method for the device is a no-op. Note it does seem to get powered-off
automatically at some point during suspend, but not directly under our
control. So we never see the PMC_D3_STS_0 register report D3 for this
I2C controller, so we should not wait for this to happen.
Not checking the D3 state of the shared I2C bus makes it possible for
these devices to properly reach S0ix states. While everything keeps working
as it should after a suspend/resume/
Regards,
Hans
