On Fri, 2018-04-13 at 14:52 +0200, Hans de Goede wrote:
> The LPSS PWM device on on Bay Trail and Cherry Trail devices has a set
> of private registers at offset 0x800, the current lpss_device_desc for
> them already sets the LPSS_SAVE_CTX flag to have these saved/restored
> over device-suspend, but the current lpss_device_desc was not setting
> the prv_offset field, leading to the regular device registers getting
> saved/restored instead.
>
> This is causing the PWM controller to no longer work, resulting in a
> black
> screen, after a suspend/resume on systems where the firmware clears
> the
> APB clock and reset bits at offset 0x804.
>
> This commit fixes this by properly setting prv_offset to 0x800 for
> the PWM devices.
>
Shouldn't be Fixes tag here?
> Signed-off-by: Hans de Goede <hdegoede@xxxxxxxxxx>
> ---
> drivers/acpi/acpi_lpss.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
> index 2bcffec8dbf0..c4ba9164e582 100644
> --- a/drivers/acpi/acpi_lpss.c
> +++ b/drivers/acpi/acpi_lpss.c
> @@ -229,11 +229,13 @@ static const struct lpss_device_desc
> lpt_sdio_dev_desc = {
>
> static const struct lpss_device_desc byt_pwm_dev_desc = {
> .flags = LPSS_SAVE_CTX,
> + .prv_offset = 0x800,
> .setup = byt_pwm_setup,
> };
>
> static const struct lpss_device_desc bsw_pwm_dev_desc = {
> .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
> + .prv_offset = 0x800,
> .setup = bsw_pwm_setup,
> };
>
--
Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
Intel Finland Oy
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