Hi Jon, >> The current SPCR code does not check the access width of the mmio, and >> uses a default of 8bit register accesses. This prevents devices that >> only do 16 or 32bit register accesses from working. By simply checking >> this field and setting the mmio string appropriately, this issue can be >> corrected. To prevent any legacy issues, the code will default to 8bit >> accesses if the value is anything but 16 or 32. > > Thanks for this. Just as an FYI I've a running discussion with Microsoft > about defining additional UART subtypes in the DBG2 for special case > UARTs. Specifically, I want to address AppliedMicro's special 8250 dw IP > that also has a non-standard clock. At this time, there is general > agreement to use the access width for some cases rather than defining > yet more subtypes - so your patch is good. > > Loc/Applied: please track this thread, incorporate feedback, and also > track the other general recent discussions of 8250 dw from this week. Thanks for forward me this patch. This patch does not work with X-Gene v1 and v2 SoC's. As BIOS SPCR encodes these info as: Bit Width: 32 Bit Offset: 0 Encoded Access Width: 01 (Byte Access) With this patch, it would use the "mmio" instead the "mmio32" as with this patch - https://patchwork.kernel.org/patch/9460959 -Loc -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
