Hi Will,
SMMU_IIDR register is broken on T99, that the reason we are using MIDR.
If using MIDR is not accepted, can we enable errata based on SMMU resource size?
some thing like below.
static bool page0_reg_only = false;
+static unsigned long arm_smmu_resource_size(void)
+{
+ if (page0_reg_only)
+ return SZ_64K;
+ else
+ return SZ_128K;
+}
+
static int arm_smmu_device_probe(struct platform_device *pdev)
{
int irq, ret;
@@ -2674,7 +2692,13 @@ static int arm_smmu_device_probe(struct
platform_device *pdev)
/* Base address */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ /*
+ * Setting page0_reg_only flag, for Cavium CN99xx implementations
+ * which doesn't support the page 1 SMMU register space.
+ */
+ if (resource_size(res) == SZ_64K)
+ page0_reg_only = true;
- if (resource_size(res) + 1 < SZ_128K) {
+ if (resource_size(res) + 1 < arm_smmu_resource_size()) {
dev_err(dev, "MMIO region too small (%pr)\n", res);
return -EINVAL;
}
Thank you,
Geetha.
On Thu, Apr 27, 2017 at 10:30 PM, Will Deacon <will.deacon@xxxxxxx> wrote:
> On Thu, Apr 27, 2017 at 05:42:37PM +0100, Mark Rutland wrote:
>> On Thu, Apr 27, 2017 at 05:16:23PM +0530, Geetha sowjanya wrote:
>> > + /*
>> > + * Override the size, for Cavium CN99xx implementations
>> > + * which doesn't support the page 1 SMMU register space.
>> > + */
>> > + cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
>> > + if (cpu_model == MIDR_THUNDERX_99XX ||
>> > + cpu_model == MIDR_BRCM_VULCAN)
>> > + size = SZ_64K;
>>
>> If you're trying to identify an SMMU erratum, identify the SMMU, not the
>> CPU it happens to be paired with this time.
>>
>> There are ID registers in the SMMU you can use to do so.
>>
>> NAK to using the CPU ID here.
>
> Agreed. I had some off-list discussion with Geetha where we agreed to use
> the "silicon ID", which I assumed was the SMMU IIDR register.
>
> Will
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