On 2015/1/22 17:26, Andy Shevchenko wrote: > On Thu, 2015-01-22 at 12:02 +0800, Li, Aubrey wrote: >> On 2015/1/21 5:50, Andy Shevchenko wrote: >>> The patch adds CHT PMC interface. This exposes all the South IP device power >>> states and S0ix states for CHT. The bit map of FUNC_DIS and D3_STS_0 registers >>> for SoCs are consistent. The D3_STS_1 and FUNC_DIS_2 registers, however, are >>> not aligned. This is fixed by splitting a common mapping on per register basis. >>> >> Should we define the bit map table completely separate for different >> platforms? My concern is, when D3_STS_0 and FUNC_DIS becomes not >> consistent in a new SoC, the implementation in this patch has to be >> rewritten completely. >> >> Defining entire bit map table for different platform introduces >> reduplicated bit definitions, but when we add a new platform in future, >> we don't need to consider the existing platforms definition, and no need >> to change code structure any longer. >> >> Thoughts? >> > > But this what I did by introducing pmc_reg_map structure per SoC. > You may or may not use previous definitions. > okay, it makes sense to me. Thanks, -Aubrey -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
