On Fri, Aug 15, 2014 at 06:42:51AM -0700, Arjan van de Ven wrote: > On 8/15/2014 6:08 AM, Ashwin Chaugule wrote: > >(b) we come up with ways to provide the bounds around a Desired value > >using the information from the platform. (long term) > > > >I briefly looked at the x86 HWP (Hardware Performance States) in the > >s/w manual again. Its essentially an implementation of CPPC. It seems > >like X86 has implemented most if not all these registers as MSRs. I'm > >really interested in knowing if anyone there is/has been working on > >using them and what they found. > > we've found that so far that there are two reasonable options > 1) Let the OS device (old style) > 2) Let the hardware decide (new style) > > 2) is there in practice today in the turbo range (which is increasingly the whole thing) > and the hardware can make decisions about power budgetting on a timescale the OS > can never even dream of, so once you give control the the hardware (with CPPC or native) > it's normally better to just get out of the way as OS. OK, so we should just forget about 'power aware scheduling' for Intel?
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