On Thu, Nov 18, 2010 at 09:34:35AM +0100, Peter Zijlstra wrote: > On Thu, 2010-11-18 at 09:14 +0800, Huang Ying wrote: > > On Wed, 2010-11-17 at 19:53 +0800, Peter Zijlstra wrote: > > > On Wed, 2010-11-17 at 19:47 +0800, huang ying wrote: > > > > On Wed, Nov 17, 2010 at 6:40 PM, Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote: > > > > > On Wed, 2010-11-17 at 10:18 +0800, Huang Ying wrote: > > > > >> > > > > >> cmpxchg has been used in that way by ftrace and perf for a long time. So > > > > >> I agree to make it a requirement on future architecture ports. > > > > > > > > > > Neither mandate an architecture do this though, only that when an > > > > > architecture wants to support either feature and has NMIs (not all archs > > > > > have NMI equivalents) it has to be safe. > > > > > > > > So we can make sure cmpxchg can be used in lock-less code on > > > > architectures with perf, irq_work or ftrace enabled? > > > > > > It had better, otherwise stuff is broken. > > > > Take a look at superh architecture cmpxchg implementation. It seems that > > cmpxchg is implemented with special instruction if CONFIG_GUSA_RB=y or > > CONFIG_CPU_SH4A=y, otherwise it is implemented with local_irq_save. Is > > it possible that superh has not PMU support if CONFIG_GUSA_RB=n and > > CONFIG_CPU_SH4A=n, so that perf work properly but no NMI safe cmpxchg in > > that situation? > > Dunno, you forgot to CC the author of that code.. I've really no clue > about SH. At the moment it's only SH-4 and SH-4A CPUs that implement PMU support, so all of these are covered by a theoretically NMI-safe cmpxchg implementation. This is more by coincidence than design, though. The only cause for concern really is SH-2A which supports hardware breakpoints (and perf events by proxy) but doesn't contain a PMU, and only uses an IRQs disabled cmpxchg for the moment. It also supports ftrace. I suppose I'll need to come up with a hack for this case.. -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
