On Tue, 2010-03-02 at 16:30 -0800, Randy Dunlap wrote:
> On 03/02/10 16:06, venkatesh.pallipadi@xxxxxxxxx wrote:
>
> {bah, more difficult to review an attachment, so no leading '>'}
Sorry. Not sure why/how you are seeing attachment issue. I used quilt
mail to send this out (I have used this method earlier as well) and I do
see patches inline .
>
> diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
> index 8c666d8..4945add 100644
> --- a/Documentation/kernel-parameters.txt
> +++ b/Documentation/kernel-parameters.txt
> @@ -749,6 +749,10 @@ and is between 256 and 4096 characters. It is defined in the file
> Default value is 0.
> Value can be changed at runtime via /selinux/enforce.
>
> + epb [X86] Control IA32_ENERGY_PERF_BIAS setting
> + "disable" - Kernel will not modify this MSR
> + <0..15> - Kernel will set this MSR to i/p static value
> +
>
>
> Should be more like:
>
> epb= [X86] Control IA32_ENERGY_PERF_BIAS setting
> Format: { disable | <0...15> }
OK. Will change.
> "disable" - Kernel will not modify this MSR
> <0..15> - Kernel will set this MSR to i/p static value
>
>
> But what is "i/p"? Use whatever word it should be, please.
I meant input. will change to something like "specified value"
> What do the values mean?
The way MSR is defined, the value is opaque. It can be used for
different optimizations in different CPUs.
> And what does IA32 have to do with this? does it not apply to x86_64?
IA32_ in any MSR name is the convention that is generally followed for
all MSRs in Intel SDM. It means that the MSR is architectural (can be
detected with CPUID or some other standard way and not CPU Model
specific.
Thanks,
Venki
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