On Thu, Mar 20, 2025 at 05:41:12PM +0000, Jonathan Cameron wrote: > Note that I've only a vague idea of who will care about this > so please do +CC others as needed. > > On x86 there is the much loved WBINVD instruction that causes a write back > and invalidate of all caches in the system. It is expensive but it is > necessary in a few corner cases. These are cases where the contents of > Physical Memory may change without any writes from the host. Whilst there > are a few reasons this might happen, the one I care about here is when > we are adding or removing mappings on CXL. So typically going from > there being actual memory at a host Physical Address to nothing there > (reads as zero, writes dropped) or visa-versa. That involves the > reprogramming of address decoders (HDM Decoders); in the near future > it may also include the device offering dynamic capacity extents. The > thing that makes it very hard to handle with CPU flushes is that the > instructions are normally VA based and not guaranteed to reach beyond > the Point of Coherence or similar. You might be able to (ab)use > various flush operations intended to ensure persistence memory but > in general they don't work either. > > So on other architectures such as ARM64 we have no instruction similar to > WBINVD but we may have device interfaces in the system that provide a way > to ensure a PA range undergoes the write back and invalidate action. This > RFC is to find a way to support those cache maintenance device interfaces. > The ones I know about are much more flexible than WBINVD, allowing > invalidation of particular PA ranges, or a much richer set of flush types > (not supported yet as not needed for upstream use cases). > > To illustrate how a solution might work, I've taken both a HiSilicon > design (slight quirk as registers overlap with existing PMU driver) > and more controversially a firmware interface proposal from ARM > (wrapped up in made up ACPI) that was dropped from the released spec > but for which the alpha spec is still available. > > Why drivers/cache? > - Mainly because it exists and smells like a reasonable place. > - Conor, you are maintainer for this currently do you mind us putting this > stuff in there? drivers/cache was just something to put the cache controller drivers we have on RISC-V that implement the various arch_dma*() callbacks in non-standard ways that made more sense than drivers/soc/<soc vendor> since the controllers are IP provided by CPU vendors. There's only two drivers here now, but I am aware of another two non-standard CMO mechanisms if the silicon with them so there'll likely be more in the future :) I'm only really maintainer of it to avoid it being another thing for Palmer to look after :) I've only skimmed this for now, but I think it is reasonable to put them here. Maybe my skim is showing, but it would not surprise me to see a driver providing both non-standard arch_dma*() callbacks as well as dealing with CXL mappings via this new class on RISC-V in the future.. Either way, I think it'd probably be a good idea to add ?you? as a co-maintainer if the directory is going to be used for your proposed interface/drivers, for what I hope is an obvious reason!
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