Hi all, I am currently working on a project involving a Xilinx FPGA connected to an x86 CPU via a PCIe root port. The Xilinx FPGA functions as a PCIe endpoint with single function capability and is programmed to emulate the Soundwire Master controller. It can be dynamically reprogrammed to emulate other interfaces as needed. Essentially, the FPGA emulates an interface and connects to the CPU via the PCIe bus. Given this setup, the BIOS does not have prior knowledge of the function implemented in the Xilinx FPGA PCIe endpoint. I have a couple of questions regarding this configuration: Is it possible to define an ACPI Device Tree representation for this type of hardware setup? Can we achieve ACPI-based device enumeration with this configuration? I would greatly appreciate any guidance or references to documentation that could help us achieve this. Thank you for your time and assistance. -- Thanks, Sekhar
