Re: [PATCH v3 3/4] cxl: Add extended linear cache address alias emission for cxl events

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To: Dave Jiang <dave.jiang@xxxxxxxxx>
Subject: Re: [PATCH v3 3/4] cxl: Add extended linear cache address alias emission for cxl events
From: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
Date: Tue, 21 Jan 2025 15:02:40 +0000
Cc: <linux-cxl@xxxxxxxxxxxxxxx>, <linux-acpi@xxxxxxxxxxxxxxx>, <rafael@xxxxxxxxxx>, <bp@xxxxxxxxx>, <dan.j.williams@xxxxxxxxx>, <tony.luck@xxxxxxxxx>, <dave@xxxxxxxxxxxx>, <alison.schofield@xxxxxxxxx>, <ira.weiny@xxxxxxxxx>, <ming.li@xxxxxxxxxxxx>
In-reply-to: <20250117173054.4147877-4-dave.jiang@intel.com>
References: <20250117173054.4147877-1-dave.jiang@intel.com> <20250117173054.4147877-4-dave.jiang@intel.com>

On Fri, 17 Jan 2025 10:28:32 -0700
Dave Jiang <dave.jiang@xxxxxxxxx> wrote:

> Add the aliased address of extended linear cache when emitting event
> trace for DRAM and general media of CXL events.
> 
> Signed-off-by: Dave Jiang <dave.jiang@xxxxxxxxx>

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>

References:
- [PATCH v3 0/4] acpi/hmat / cxl: Add exclusive caching enumeration and RAS support
  - From: Dave Jiang
- [PATCH v3 3/4] cxl: Add extended linear cache address alias emission for cxl events
  - From: Dave Jiang

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