On 12/2/2024 09:59, Peter Zijlstra wrote:
On Sat, Nov 30, 2024 at 08:07:00AM -0600, Mario Limonciello wrote:
From: Perry Yuan <perry.yuan@xxxxxxx>
Incorporate a mechanism within the context switching code to reset
the hardware history for AMD processors. Specifically, when a task
is switched in, the class ID was read and reset the hardware workload
classification history of CPU firmware and then it start to trigger
workload classification for the next running thread.
Signed-off-by: Perry Yuan <perry.yuan@xxxxxxx>
Co-developed-by: Mario Limonciello <mario.limonciello@xxxxxxx>
Signed-off-by: Mario Limonciello <mario.limonciello@xxxxxxx>
---
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 226472332a70d..371e0e8f987fa 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -709,6 +709,10 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
/* Load the Intel cache allocation PQR MSR. */
resctrl_sched_in(next_p);
+ /* Reset hw history on AMD CPUs */
+ if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS))
+ wrmsrl(AMD_WORKLOAD_HRST, 0x1);
+
return prev_p;
}
BTW, how many cycles for this WRMSR ?
When I measured it the average delay was ~119ns with a wider range of
delays (standard deviation was 25% greater).
And, as already stated, I'm failing to find the actual classification
code, but assuming that's RDMSR(s?), how much for them?
As mentioned on patch 1 comments the current patch series doesn't use
any classification data produced by the hardware.
