On Wed, Nov 06, 2024 at 10:35:07PM -0400, Jason Gunthorpe wrote: > I agree the kdoc does not describe what the baseline actually is. Nicolin worked on this, here is a more detailed kdoc: /** * struct iommu_hw_info_arm_smmuv3 - ARM SMMUv3 hardware information * (IOMMU_HW_INFO_TYPE_ARM_SMMUV3) * * @flags: Must be set to 0 * @__reserved: Must be 0 * @idr: Implemented features for ARM SMMU Non-secure programming interface * @iidr: Information about the implementation and implementer of ARM SMMU, * and architecture version supported * @aidr: ARM SMMU architecture version * * For the details of @idr, @iidr and @aidr, please refer to the chapters * from 6.3.1 to 6.3.6 in the SMMUv3 Spec. * * This reports the raw HW capability, and not all bits are meaningful to be * read by userspace. Only the following fields should be used: * * idr[0]: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN , CD2L, ASID16, TTF * idr[1]: SIDSIZE, SSIDSIZE * idr[3]: BBML, RIL * idr[5]: VAX, GRAN64K, GRAN16K, GRAN4K * * - S1P should be assumed to be true if a NESTED HWPT can be created * - VFIO/iommufd only support platforms with COHACC, it should be assumed to be * true. * - ATS is a per-device property. If the VMM describes any devices as ATS * capable in ACPI/DT it should set the corresponding idr. * * This list may expand in future (eg E0PD, AIE, PBHA, D128, DS etc). It is * important that VMMs do not read bits outside the list to allow for * compatibility with future kernels. Several features in the SMMUv3 * architecture are not currently supported by the kernel for nesting: HTTU, * BTM, MPAM and others. */ This focuses on stuff we can actually test and gives a path to test and confirm a no-code update to future stuff. The future list (E0PD/etc) reflects things the current kernel doesn't use. Our naive read of the spec suggests they are probably fine to just read the raw HW IDR. When someone implements guest kernel support, does a detailed spec read, and crucially tests them - then we can update the comment and have immediate support. HTTU, BTM, and others like that will need additional bits outside the IDR if someone wishes to enable them. Jason
