On 10/17/24 9:59 AM, Jonathan Cameron wrote: > On Thu, 17 Oct 2024 16:46:35 +0000 > "Luck, Tony" <tony.luck@xxxxxxxxx> wrote: > >>> What does the I/O hole correspond to in the system? >> >> PCIe mmio mapped space. 32-bit devices must have addresses below 4G >> so X86 systems have a physical memory map that looks like: >> >> 0 - 2G: RAM >> 2G-4G: MMIO >> 4G-end of memory: RAM >> end of memory-infinity: 64-bit MMIO >> >> Depending on how much MMIO there is different systems put the >> dividing line at other addresses than 2G. > > Ah, thanks. So this weird cache setup might be not quite linear > module N aliases as described in the ACPI spec (System vs host > physical addresses I guess). Well, as long as the cache range does not overlap the MMIO hole. I'm not coming up with an elegant way to enumerate the MMIO hole and looking for ideas/suggestions on how to do it nicely. > > Had wrong mental model :( > > Ouch. > > >> >> -Tony >> >
