On Thu, May 09, 2024 at 03:32:59PM +0800, Yunhui Cui wrote: > Before cacheinfo can be built correctly, we need to initialize level > and type. Since RISC-V currently does not have a register group that > describes cache-related attributes like ARM64, we cannot obtain them > directly, so now we obtain cache leaves from the ACPI PPTT table > (acpi_get_cache_info()) and set the cache type through split_levels. > > Suggested-by: Jeremy Linton <jeremy.linton@xxxxxxx> > Suggested-by: Sudeep Holla <sudeep.holla@xxxxxxx> I am not sure why you have not added my reviewed-by as I was happy with v3 onwards IIRC. Anyways, I will give it again 😄 Reviewed-by: Sudeep Holla <sudeep.holla@xxxxxxx> -- Regards, Sudeep
