Hi Palmer, Gentle ping... On Fri, May 3, 2024 at 12:37 AM Conor Dooley <conor@xxxxxxxxxx> wrote: > > On Thu, Apr 18, 2024 at 11:43:29AM +0800, Yunhui Cui wrote: > > Before cacheinfo can be built correctly, we need to initialize level > > and type. Since RSIC-V currently does not have a register group that > > describes cache-related attributes like ARM64, we cannot obtain them > > directly, so now we obtain cache leaves from the ACPI PPTT table > > (acpi_get_cache_info()) and set the cache type through split_levels. > > > > Suggested-by: Jeremy Linton <jeremy.linton@xxxxxxx> > > Suggested-by: Sudeep Holla <sudeep.holla@xxxxxxx> > : Signed-off-by: Yunhui Cui <cuiyunhui@xxxxxxxxxxxxx> > > I'm not an ACPI head, so whether or not the table is valid on RISC-V or > w/e I do not know, but the code here looks sane to me, so > Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > > Cheers, > Conor. Thanks, Yunhui
