"Rafael J. Wysocki" <rafael@xxxxxxxxxx> writes: > On Mon, Apr 15, 2024 at 7:01 PM Sunil V L <sunilvl@xxxxxxxxxxxxxxxx> wrote: >> >> This series adds support for the below ECR approved by ASWG. >> 1) MADT - https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view?usp=sharing >> >> The series primarily enables irqchip drivers for RISC-V ACPI based >> platforms. >> >> The series can be broadly categorized like below. >> >> 1) PCI ACPI related functions are migrated from arm64 to common file so >> that we don't need to duplicate them for RISC-V. >> >> 2) Added support for re-ordering the probe of interrupt controllers when >> IRQCHIP_ACPI_DECLARE is used. >> >> 3) To ensure probe order between interrupt controllers and devices, >> implicit dependency is created similar to when _DEP is present. >> >> 4) When PNP devices like Generic 16550A UART, have the dependency on the >> interrupt controller, they will not be added to PNP data structures. So, >> added second phase of pnpacpi_init to handle this. >> >> 5) ACPI support added in RISC-V interrupt controller drivers. >> >> This series is still kept as RFC to seek feedback on above design >> changes. Looking forward for the feedback! > > I've looked at the patches and I don't see anything deeply concerning > in them from the ACPI core code perspective. > > The changes look reasonably straightforward to me. Sunil, given Rafael's input, it sounds like it's time for a patch proper. This is really the missing piece to make ACPI usable on RISC-V! Thanks for the nice work! Björn FWIW, Tested-by: Björn Töpel <bjorn@xxxxxxxxxxxx>
