Re: local bus enumeration beyond a PCI device

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Thu, Apr 18, 2024 at 12:24:06AM +0000, Chris Packham kirjoitti:
> Hi,
> We've got a custom x86_64 based design that is using an ASIX9100 to 
> provide a PCI to local bus bridge. Attached to that local bus is an FPGA 
> which mostly provides some GPIOs accessed via registers on the local 
> bus. Right now we've got a custom driver that bundles everything 
> together so effectively we've got a PCI device that provides GPIOs.
> But as things can change based on the FPGA program I'd like some 
> flexibility to treat it separately from the PCI bridge.

Why? AFAIU the architecture, you have an FPGA with a real PCI bridge / switch,
no? If it's the case, the software shouldn't care if the respective IP comes
from FPGA or SoC.

> So really I'd 
> like to have a PCI device driver for the ASIX9100 that provides a local 
> bus controller and a (platform?) driver for the FPGA that provides the 
> GPIOs where I can have different compatibles for the different 
> implementations.
> Then in the ACPI overlay I'd have something like
>      Scope (\_SB.PCI0.D0B0)
>      {
>          Device (ASIX)
>          {
>              Name (_ADR, 0x0000)
>              Device (FPGA)
>              {
>                          Name (_HID, "PRP0001")
>                          Name (_DSD, Package ()
>                          {
> ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
>                                      Package ()
>                                      {
>                                                  Package () { 
> "compatible", "my-platform-driver-for-fpga" },
>                                      }
>                          })
>              }
>          }
>      }
>     Scope(\_SB)
>     {
>          Device(OTHR)
>          {
>              GpioIo (Exclusive, PullUp, 0, 0, IoRestrictionInputOnly, 
> "\\_SB.PCI0.D0B0.ASIX.FPGA",) { 0 }
>          }
>     }
> Is it even possible to register a host controller for another platform bus?

AFAIK there is an FPGA framework in the kernel and the idea is that each FPGA
configuration provides a complimentary DT to describe the hardware setup. As
Bjorn Cc'ed this to Herve you may get the answer on what's going on there much
better as I'm not involved in the development of that topic.

With Best Regards,
Andy Shevchenko

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