> -----Original Message----- > From: fan <nifan.cxl@xxxxxxxxx> > Sent: Monday, March 4, 2024 8:38 AM > To: Ho-Ren (Jack) Chuang <horenchuang@xxxxxxxxxxxxx> > Cc: Hao Xiang <hao.xiang@xxxxxxxxxxxxx>; Gregory Price > <gourry.memverge@xxxxxxxxx>; aneesh.kumar@xxxxxxxxxxxxx; > mhocko@xxxxxxxx; tj@xxxxxxxxxx; john@xxxxxxxxxxxxxx; Eishan Mirakhur > <emirakhur@xxxxxxxxxx>; Vinicius Tavares Petrucci > <vtavarespetr@xxxxxxxxxx>; Ravis OpenSrc <Ravis.OpenSrc@xxxxxxxxxx>; > Alistair Popple <apopple@xxxxxxxxxx>; Rafael J. Wysocki > <rafael@xxxxxxxxxx>; Len Brown <lenb@xxxxxxxxxx>; Andrew Morton > <akpm@xxxxxxxxxxxxxxxxxxxx>; Dave Jiang <dave.jiang@xxxxxxxxx>; Dan > Williams <dan.j.williams@xxxxxxxxx>; Jonathan Cameron > <Jonathan.Cameron@xxxxxxxxxx>; Huang Ying <ying.huang@xxxxxxxxx>; > linux-acpi@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux- > mm@xxxxxxxxx; Ho-Ren (Jack) Chuang <horenc@xxxxxx>; Ho-Ren (Jack) > Chuang <horenchuang@xxxxxxxxx>; linux-cxl@xxxxxxxxxxxxxxx; qemu- > devel@xxxxxxxxxx > Subject: [EXT] Re: [PATCH v1 0/1] Improved Memory Tier Creation for CPUless > NUMA Nodes > > CAUTION: EXTERNAL EMAIL. Do not click links or open attachments unless > you recognize the sender and were expecting this message. > > > On Fri, Mar 01, 2024 at 08:22:44AM +0000, Ho-Ren (Jack) Chuang wrote: > > The memory tiering component in the kernel is functionally useless for > > CPUless memory/non-DRAM devices like CXL1.1 type3 memory because the > nodes > > are lumped together in the DRAM tier. > > > https://lore.k/ > ernel.org%2Flinux- > mm%2FPH0PR08MB7955E9F08CCB64F23963B5C3A860A%40PH0PR08MB7955 > .namprd08.prod.outlook.com%2FT%2F&data=05%7C02%7Csthanneeru.open > src%40micron.com%7Cc4f03409bf454cca29d008dc3bf853d0%7Cf38a5ecd281 > 34862b11bac1d563c806f%7C0%7C0%7C638451185012848960%7CUnknown > %7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW > wiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata=syvhw1w8%2BoC6ss4%2Bu2X > HjBuyrpwFK1hIefopgVbRy7g%3D&reserved=0 > Referring to the following use case from above patch? -- 1. Useful to move cxl nodes to the right tiers from userspace, when the hardware fails to assign the tiers correctly based on memorytypes. On some platforms we have observed cxl memory being assigned to the same tier as DDR memory. This is arguably a system firmware bug, but it is true that tiers represent *ranges* of performance. and we believe it's important for the system operator to have the ability to override bad firmware or OS decisions about tier assignment as a fail-safe against potential bad outcomes. -- > Is this the right patchset you want to refer to? It is about node > migration between tiers, how is it related to the context here? > > Fan > > > > > This patchset automatically resolves the issues. It delays the initialization > > of memory tiers for CPUless NUMA nodes until they obtain HMAT > information > > at boot time, eliminating the need for user intervention. > > If no HMAT specified, it falls back to using `default_dram_type`. > > > > Example usecase: > > We have CXL memory on the host, and we create VMs with a new system > memory > > device backed by host CXL memory. We inject CXL memory performance > attributes > > through QEMU, and the guest now sees memory nodes with performance > attributes > > in HMAT. With this change, we enable the guest kernel to construct > > the correct memory tiering for the memory nodes. > > > > Ho-Ren (Jack) Chuang (1): > > memory tier: acpi/hmat: create CPUless memory tiers after obtaining > > HMAT info > > > > drivers/acpi/numa/hmat.c | 3 ++ > > include/linux/memory-tiers.h | 6 +++ > > mm/memory-tiers.c | 76 ++++++++++++++++++++++++++++++++---- > > 3 files changed, 77 insertions(+), 8 deletions(-) > > > > -- > > Hao Xiang and Ho-Ren (Jack) Chuang > >
