"Ho-Ren (Jack) Chuang" <horenchuang@xxxxxxxxxxxxx> writes: > The memory tiering component in the kernel is functionally useless for > CPUless memory/non-DRAM devices like CXL1.1 type3 memory because the nodes > are lumped together in the DRAM tier. > https://lore.kernel.org/linux-mm/PH0PR08MB7955E9F08CCB64F23963B5C3A860A@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx/T/ I think that it's unfair to call it "useless". Yes, it doesn't work if the CXL memory device are not enumerate via drivers/dax/kmem.c. So, please be specific about in which cases it doesn't work instead of too general "useless". > This patchset automatically resolves the issues. It delays the initialization > of memory tiers for CPUless NUMA nodes until they obtain HMAT information > at boot time, eliminating the need for user intervention. > If no HMAT specified, it falls back to using `default_dram_type`. > > Example usecase: > We have CXL memory on the host, and we create VMs with a new system memory > device backed by host CXL memory. We inject CXL memory performance attributes > through QEMU, and the guest now sees memory nodes with performance attributes > in HMAT. With this change, we enable the guest kernel to construct > the correct memory tiering for the memory nodes. > > Ho-Ren (Jack) Chuang (1): > memory tier: acpi/hmat: create CPUless memory tiers after obtaining > HMAT info > > drivers/acpi/numa/hmat.c | 3 ++ > include/linux/memory-tiers.h | 6 +++ > mm/memory-tiers.c | 76 ++++++++++++++++++++++++++++++++---- > 3 files changed, 77 insertions(+), 8 deletions(-) -- Best Regards, Huang, Ying
