On Tue, 20 Feb 2024 16:12:32 -0700 Dave Jiang <dave.jiang@xxxxxxxxx> wrote: > In order to compute access0 and access1 classes for CXL memory, 2 levels > of generic port information must be stored. Access0 will indicate the > generic port access coordinates to the closest initiator and access1 > will indicate the generic port access coordinates to the cloest CPU. > > Cc: Rafael J. Wysocki <rafael@xxxxxxxxxx> > Signed-off-by: Dave Jiang <dave.jiang@xxxxxxxxx> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
