Hi Rafael, Please review patches 1-4,10,11 and ack if they look ok to you. Thank you! Hi Greg, Please review patch 2 and 11 and ack the numa node bits if they look ok to you. Thank you! v4: - Introduce access class 0 and 1 for CXL access coordinates. - See individual patches for detailed change log if applicable. v3: - Make attributes not visible if no data. (Jonathan) - Fix documentation verbiage. (Jonathan) - Check against read bandwidth instead of write bandwidth due to future RO devices. (Jonathan) - Export node_set_perf_attrs() to all namespaces. (Jonathan) - Remove setting of coordinate access level 1. (Jonathan) v2: - Move calculation function to core/cdat.c due to QTG series changes - Make cxlr->coord static (Dan) - Move calculation to cxl_region_attach to be under cxl_dpa_rwsem (Dan) - Normalize perf latency numbers to nanoseconds (Brice) - Update documentation with units and initiator details (Brice, Dan) - Fix notifier return values (Dan) - Use devm_add_action_or_reset() to unregister memory notifier (Dan) This series adds support for computing the performance data of a CXL region and also updates the performance data to the NUMA node. This series depends on the CXL QOS class series that's pending 6.8 pull request. CXL memory devices already attached before boot are enumerated by the BIOS. The SRAT and HMAT tables are properly setup to including memory regions enumerated from those CXL memory devices. For regions not programmed or a hot-plugged CXL memory device, the BIOS does not have the relevant information and the performance data has to be caluclated by the driver post region assembly. According to numaperf documentation [1] there are 2 access classes defined for performance between an initiator node and a memory target node. Access class "0" describes attributes between a memory target and the highest performing initator local to the target. In this case the initiator can be a CPU or an I/O initiator such as a GPU or NIC. Access class "1" describes attributes between a memory target and the nearest CPU node. Both access classes are calculated for the CXL memory target and updated for NUMA nodes through HMAT_REPORTING code or directly depending on if the NUMA node is described by the ACPI SRAT table. Recall from [2] that the performance data for the ranges of a CXL memory device is computed and cached. A CXL memory region can be backed by one or more devices. Thus the performance data would be the aggregated bandwidth of all devices that back a region and the worst latency out of all devices backing the region. See git branch [3] for convenience. [1]: https://www.kernel.org/doc/Documentation/admin-guide/mm/numaperf.rst [2]: https://lore.kernel.org/linux-cxl/170319606771.2212653.5435838660860735129.stgit@djiang5-mobl3/ [3]: https://git.kernel.org/pub/scm/linux/kernel/git/djiang/linux.git/log/?h=cxl-hmem-report --- Dave Jiang (11): ACPI: HMAT: Remove register of memory node for generic target base/node / ACPI: Enumerate node access class for 'struct access_coordinate' ACPI: HMAT: Introduce 2 levels of generic port access class ACPI: HMAT / cxl: Add retrieval of generic port coordinates for both access classes cxl: Split out combine_coordinates() for common shared usage cxl: Split out host bridge access coordinates cxl: Set cxlmd->endpoint before adding port device cxl/region: Calculate performance data for a region cxl/region: Add sysfs attribute for locality attributes of CXL regions cxl/region: Add memory hotplug notifier for cxl region cxl/region: Deal with numa nodes not enumarated by SRAT Documentation/ABI/testing/sysfs-bus-cxl | 60 +++++++ drivers/acpi/numa/hmat.c | 86 +++++++--- drivers/acpi/numa/srat.c | 11 ++ drivers/base/node.c | 7 +- drivers/cxl/acpi.c | 8 +- drivers/cxl/core/cdat.c | 142 ++++++++++++++-- drivers/cxl/core/core.h | 4 + drivers/cxl/core/port.c | 44 +++-- drivers/cxl/core/region.c | 216 ++++++++++++++++++++++++ drivers/cxl/cxl.h | 15 +- include/linux/acpi.h | 10 ++ include/linux/memory.h | 1 + include/linux/node.h | 18 +- 13 files changed, 565 insertions(+), 57 deletions(-) --
