Ben Cheatham wrote: > Update EINJ kernel document to include how to inject CXL protocol error > types, build the kernel to include CXL error types, and give an example > injection. > > Signed-off-by: Ben Cheatham <Benjamin.Cheatham@xxxxxxx> > --- > .../firmware-guide/acpi/apei/einj.rst | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/Documentation/firmware-guide/acpi/apei/einj.rst b/Documentation/firmware-guide/acpi/apei/einj.rst > index d6b61d22f525..a8f26845682a 100644 > --- a/Documentation/firmware-guide/acpi/apei/einj.rst > +++ b/Documentation/firmware-guide/acpi/apei/einj.rst > @@ -181,6 +181,25 @@ You should see something like this in dmesg:: > [22715.834759] EDAC sbridge MC3: PROCESSOR 0:306e7 TIME 1422553404 SOCKET 0 APIC 0 > [22716.616173] EDAC MC3: 1 CE memory read error on CPU_SrcID#0_Channel#0_DIMM#0 (channel:0 slot:0 page:0x12345 offset:0x0 grain:32 syndrome:0x0 - area:DRAM err_code:0001:0090 socket:0 channel_mask:1 rank:0) > > +CXL error types are supported from ACPI 6.5 onwards. These error types > +are not available in the legacy interface at /sys/kernel/debug/apei/einj, > +and are instead at /sys/kernel/debug/cxl/. There is a file under debug/cxl > +called "einj_type" that is analagous to available_error_type under debug/cxl. s/analagous/analogous/ Other than that, looks good.
