> From: Rafael J. Wysocki <rafael@xxxxxxxxxx> > Sent: Friday, September 15, 2023 11:21 AM > To: Salil Mehta <salil.mehta@xxxxxxxxxx> > Cc: Rafael J. Wysocki <rafael@xxxxxxxxxx>; Russell King (Oracle) > <linux@xxxxxxxxxxxxxxx>; Ard Biesheuvel <ardb@xxxxxxxxxx>; Jonathan Cameron > <jonathan.cameron@xxxxxxxxxx>; James Morse <james.morse@xxxxxxx>; linux- > pm@xxxxxxxxxxxxxxx; loongarch@xxxxxxxxxxxxxxx; linux-acpi@xxxxxxxxxxxxxxx; > linux-arch@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-arm- > kernel@xxxxxxxxxxxxxxxxxxx; linux-riscv@xxxxxxxxxxxxxxxxxxx; > kvmarm@xxxxxxxxxxxxxxx; x86@xxxxxxxxxx; Jean-Philippe Brucker <jean- > philippe@xxxxxxxxxx>; jianyong.wu@xxxxxxx; justin.he@xxxxxxx > Subject: Re: [RFC PATCH v2 27/35] ACPICA: Add new MADT GICC flags fields > [code first?] > > On Fri, Sep 15, 2023 at 11:34 AM Salil Mehta <salil.mehta@xxxxxxxxxx> > wrote: > > > > > > > From: Rafael J. Wysocki <rafael@xxxxxxxxxx> > > > Sent: Friday, September 15, 2023 9:45 AM > > > To: Russell King (Oracle) <linux@xxxxxxxxxxxxxxx> > > > Cc: Salil Mehta <salil.mehta@xxxxxxxxxx>; Ard Biesheuvel <ardb@xxxxxxxxxx>; > > > Jonathan Cameron <jonathan.cameron@xxxxxxxxxx>; James Morse > > > <james.morse@xxxxxxx>; linux-pm@xxxxxxxxxxxxxxx; loongarch@xxxxxxxxxxxxxxx; > > > linux-acpi@xxxxxxxxxxxxxxx; linux-arch@xxxxxxxxxxxxxxx; linux- > > > kernel@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux- > > > riscv@xxxxxxxxxxxxxxxxxxx; kvmarm@xxxxxxxxxxxxxxx; x86@xxxxxxxxxx; > Jean- > > > Philippe Brucker <jean-philippe@xxxxxxxxxx>; jianyong.wu@xxxxxxx; > > > justin.he@xxxxxxx > > > Subject: Re: [RFC PATCH v2 27/35] ACPICA: Add new MADT GICC flags > fields > > > [code first?] > > > > > > On Fri, Sep 15, 2023 at 9:09 AM Russell King (Oracle) > > > <linux@xxxxxxxxxxxxxxx> wrote: > > > > > > > > On Fri, Sep 15, 2023 at 02:29:13AM +0000, Salil Mehta wrote: > > > > > On x86, during init, if the MADT entry for LAPIC is found to be > > > > > online-capable and is enabled as well then possible and present > > > > > > > > Note that the ACPI spec says enabled + online-capable isn't defined. > > > > > > > > "The information conveyed by this bit depends on the value of the > > > > Enabled bit. If the Enabled bit is set, this bit is reserved and > > > > must be zero." > > > > > > > > So, if x86 is doing something with the enabled && online-capable > > > > state (other than ignoring the online-capable) then technically it > > > > is doing something that the spec doesn't define > > > > > > And so it is wrong. > > > > > > Or maybe, specification has not been updated yet. code-first? > > Well, if you are aware of any change requests related to this and > posted as code-first, please let me know. I am not aware of any on x86. Maybe we can do it on ARM first and let other Arch pitch-in their objection later? Afterall, there is a legitimate use-case in case of ARM. Having mutually exclusive bits breaks certain use-cases and we have to do the tradeoffs. This can be done in parallel while other patches are getting reviewed and momentarily living with the tradeoffs till specification is sorted. But of course it depends upon what other stake holders and most importantly what ARM Arch people think of it. Thanks Salil.
